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docchip hardware accelerator  (Xilinx Inc)

 
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    Structured Review

    Xilinx Inc docchip hardware accelerator
    The system-level architecture of the i <t>DocChip</t> binarization step.
    Docchip Hardware Accelerator, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
    https://www.bioz.com/result/docchip hardware accelerator/product/Xilinx Inc
    Average 90 stars, based on 1 article reviews
    docchip hardware accelerator - by Bioz Stars, 2026-04
    90/100 stars

    Images

    1) Product Images from "i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing"

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    Journal: Journal of Imaging

    doi: 10.3390/jimaging7090175

    The system-level architecture of the i DocChip binarization step.
    Figure Legend Snippet: The system-level architecture of the i DocChip binarization step.

    Techniques Used:

    The system-level architecture of the i DocChip text and image segmentation step.
    Figure Legend Snippet: The system-level architecture of the i DocChip text and image segmentation step.

    Techniques Used:

    The system-level architecture of the i DocChip text line extraction step.
    Figure Legend Snippet: The system-level architecture of the i DocChip text line extraction step.

    Techniques Used:

    The system-level architecture of the i DocChip text line recognition step.
    Figure Legend Snippet: The system-level architecture of the i DocChip text line recognition step.

    Techniques Used:

    Hardware-software partitioning of the binarization process for the i DocChip system.
    Figure Legend Snippet: Hardware-software partitioning of the binarization process for the i DocChip system.

    Techniques Used: Software

    Hardware-software partitioning of text and image segmentation for the i DocChip system.
    Figure Legend Snippet: Hardware-software partitioning of text and image segmentation for the i DocChip system.

    Techniques Used: Software

    Hardware-software partitioning of text line extraction for the i DocChip system.
    Figure Legend Snippet: Hardware-software partitioning of text line extraction for the i DocChip system.

    Techniques Used: Software

    The system-level architecture of the i DocChip binarization step.
    Figure Legend Snippet: The system-level architecture of the i DocChip binarization step.

    Techniques Used:

    The system-level architecture of the i DocChip text line recognition step.
    Figure Legend Snippet: The system-level architecture of the i DocChip text line recognition step.

    Techniques Used:

    Character-level accuracy of Cloud Vision OCR and i DocChip OCR.
    Figure Legend Snippet: Character-level accuracy of Cloud Vision OCR and i DocChip OCR.

    Techniques Used:

    Resource utilization of the hardware implementation for the end-to-end OCR i DocChip system (this work) compared to the total resource utilization of the previous separately implemented pipeline steps [ <xref ref-type= 26 , 27 , 28 , 29 ] using Zynq 7045 device @ 166MHz." title="... the hardware implementation for the end-to-end OCR i DocChip system (this work) compared to the ..." property="contentUrl" width="100%" height="100%"/>
    Figure Legend Snippet: Resource utilization of the hardware implementation for the end-to-end OCR i DocChip system (this work) compared to the total resource utilization of the previous separately implemented pipeline steps [ 26 , 27 , 28 , 29 ] using Zynq 7045 device @ 166MHz.

    Techniques Used:

    Power vs. runtime comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. Runtime is given per image. Single-threaded and multi-threaded implementations are represented as ST and MT . The grid lines show energy consumption in Joules (J).
    Figure Legend Snippet: Power vs. runtime comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. Runtime is given per image. Single-threaded and multi-threaded implementations are represented as ST and MT . The grid lines show energy consumption in Joules (J).

    Techniques Used:

    Power vs. FPS comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. The grid lines show energy efficiency in FPS/W.
    Figure Legend Snippet: Power vs. FPS comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. The grid lines show energy efficiency in FPS/W.

    Techniques Used:



    Similar Products

    docchip hardware accelerator  (Xilinx Inc)
    90
    Xilinx Inc docchip hardware accelerator
    The system-level architecture of the i <t>DocChip</t> binarization step.
    Docchip Hardware Accelerator, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
    https://www.bioz.com/result/docchip hardware accelerator/product/Xilinx Inc
    Average 90 stars, based on 1 article reviews
    docchip hardware accelerator - by Bioz Stars, 2026-04
    90/100 stars
    		  Buy from Supplier

    Image Search Results


    The system-level architecture of the i DocChip binarization step.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: The system-level architecture of the i DocChip binarization step.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    The system-level architecture of the i DocChip text and image segmentation step.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: The system-level architecture of the i DocChip text and image segmentation step.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    The system-level architecture of the i DocChip text line extraction step.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: The system-level architecture of the i DocChip text line extraction step.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    The system-level architecture of the i DocChip text line recognition step.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: The system-level architecture of the i DocChip text line recognition step.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    Hardware-software partitioning of the binarization process for the i DocChip system.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: Hardware-software partitioning of the binarization process for the i DocChip system.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques: Software

    Hardware-software partitioning of text and image segmentation for the i DocChip system.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: Hardware-software partitioning of text and image segmentation for the i DocChip system.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques: Software

    Hardware-software partitioning of text line extraction for the i DocChip system.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: Hardware-software partitioning of text line extraction for the i DocChip system.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques: Software

    The system-level architecture of the i DocChip binarization step.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: The system-level architecture of the i DocChip binarization step.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    The system-level architecture of the i DocChip text line recognition step.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: The system-level architecture of the i DocChip text line recognition step.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    Character-level accuracy of Cloud Vision OCR and i DocChip OCR.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: Character-level accuracy of Cloud Vision OCR and i DocChip OCR.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    Resource utilization of the hardware implementation for the end-to-end OCR i DocChip system (this work) compared to the total resource utilization of the previous separately implemented pipeline steps [ <xref ref-type= 26 , 27 , 28 , 29 ] using Zynq 7045 device @ 166MHz." width="100%" height="100%">

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: Resource utilization of the hardware implementation for the end-to-end OCR i DocChip system (this work) compared to the total resource utilization of the previous separately implemented pipeline steps [ 26 , 27 , 28 , 29 ] using Zynq 7045 device @ 166MHz.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    Power vs. runtime comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. Runtime is given per image. Single-threaded and multi-threaded implementations are represented as ST and MT . The grid lines show energy consumption in Joules (J).

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: Power vs. runtime comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. Runtime is given per image. Single-threaded and multi-threaded implementations are represented as ST and MT . The grid lines show energy consumption in Joules (J).

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques:

    Power vs. FPS comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. The grid lines show energy efficiency in FPS/W.

    Journal: Journal of Imaging

    Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

    doi: 10.3390/jimaging7090175

    Figure Lengend Snippet: Power vs. FPS comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. The grid lines show energy efficiency in FPS/W.

    Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

    Techniques: